1. Technical Field
An embodiment of the present invention relates to a clock and data recovery circuit that recovers a clock from the NRZ (Non-Return-to-Zero) type of non-periodic received data in a high speed serial communication and recovers data using recovered clock signal.
2. Background Art
A typical clock and data recovery circuit generates from an inputted data signal a clock signal that is synchronized to a data signal to recover a data signal and a clock signal. The clock and data recovery circuit is widely used for data transmission in a LAN, wireless/wired communication, optical communication, disk drive, etc.
The clock and data recovery circuit is commonly designed by selecting one phase detector (e.g., a binary phase detector or a linear phase detector). When one phase detector is used, any problem inherent in the phase detector hinders the clock and data recovery circuit from operating properly.
Specifically, in case a binary phase detector is used, the gain of the phase detector is changed according to the jitter of the recovered clock and received data, and in case a linear phase detector is used, the phase offset between the received data and the recovered clock due to a mismatch of up/down currents of a charge pump and other mismatches resulted from various causes is relatively large because of the small gain of the phase detector.
Accordingly, studies have been needed for a clock and data recovery circuit that can allow a constant gain of a phase detector and can compensate for a phase offset between the received data and recovered clock.